The increasing complexity of surface-mount interconnection technology and integrated circuit packaging techniques presents an ever increasing problem of testing integrated circuits and printed circuit boards (system logic board). The main goals of these tests are to confirm the correct interconnection of components, the proper function of each component and the proper interaction of components in a product. To achieve these goals, the international Joint Test Action Group (JTAG) created the IEEE 1149.1 (1990) test access port and boundary-scan architecture standard (JTAG standard), which is incorporated herein in its entirety by reference. The primary goal of this standard is to ensure that circuit components contain a common denominator of test circuitry.
One implementation of the JTAG standard incorporates test access port (TAP) for accessing the test support functions built into an integrated circuit component or a system logic board. The TAP serves as a diagnostic interface. The TAP is composed, as minimum, of three input connections and one output connection as defined by the IEEE 1149.1 standard. The three input connections are defined as test clock input (TCK), test data input (TDI), and test mode select input (TMS), while the output connection is defined as test data output (TDO). In addition, an optional fourth input connection defined as test reset input (TRST*) is permitted by the standard for initialization of the TAP controller. For a detailed discussion of these signal connections, see the IEEE 1149.1 standard (1990).
The implementation further incorporates shift register segments into an integrated circuit component for serial boundary-scan testing. The shift register segments are daisy chained to form a path around the periphery of the integrated circuit component. In turn, a number of circuit components are typically chained together so that test data is shifted serially into and through a plurality of circuit components. The serial test data (scan path image) follows a predefined path and exits the circuit components with the test data altered by the circuit functions. A controller compares the altered test data with expected known results and determines whether the circuit components are in good working order. If the test data produces an unexpected result, then a malfunction has been detected within the circuit.
Specifically, a scan cycle either shifts the content of the TAP's instruction register or it shifts the contents of the shift register based circuits on the selected test data register path. The instruction register allows instruction to be serially entered into the test logic. Each instruction defines the set of test data registers that may operate while that instructions is current, and the instruction also selects the test data register path to shift by a subsequent data register scan cycle. The selected test data register path is typically a bank of shift register based circuits used for conditioning values and receiving stimuli.
The flexibility of this architecture permits the daisy chaining of IEEE 1149.1 compliant circuit components both within as well as across system logic boards. A plurality of system logic boards can be efficiently tested by propagating a long scan path image through the integrated circuit components of a system logic board and then directing the scan path image to the next daisy chained system logic board. Finally, the serial data is returned to the controller from the last circuit component on the last daisy chained system logic board.
Although the JTAG standard increases the efficiency and reduces the cost of component and logic board testing, the daisy chaining scheme is computationally expensive as the number of circuit components increases within a system logic board. In order to access a particular register of a circuit component within a daisy chain, the controller must construct a long data string (scan path image) having a length that equals the sum of all the registers of the chained components.
To illustrate, if the controller needs to read and write to a 3-bit wide instruction register of the 10th chained component from a daisy chain of one hundred (100) components, the controller needs to read 300 bits of data (100 components with each having a 3-bit wide instruction register) into system memory. The controller obtains the relevant three bits of data from the system memory by applying a conventional bit extraction technique. Subsequently, in order to write to the selected instruction register, the controller reconstructs a new 300 bit scan path image having three new bits of data. The new scan path image is then shifted serially back to the daisy chained components. Thus, the read/write operation of three (3) bits of data requires the shifting of 600 bits of data to and from the system memory. As the complexity and quantity of circuit components and logic boards increase, the daisy chaining scheme creates a large computational overhead.
Another deficiency of current systems involves the use of "system calls" by software applications. Generally, in order for a software application to execute a test sequence (i.e. performing a plurality of shift operations), the software application may need to issue a plurality of system calls. System calls provide the interface between a process and the operating system. System calls are roughly grouped into five major categories: process control, file manipulation, device manipulation, information maintenance, and communication.
In order for an application to access and perform I/O operations on a target device hardware such as a system logic board, a system call path is generally established through the operating system or "kernel". Such system calls require the use of interrupts which have an overhead on the order of hundreds of microseconds. Conversely, the operation of shifting a short string of data typically has an overhead on the order of several microseconds. Thus, the overhead of the input/output (I/O) requests actually exceeds the overhead of the I/O operation itself (i.e. a shift operation).
Therefore, a need exists in the art for a system and method that optimizes shift operations by reducing the computational overhead and the number of full scan path shifts associated with accessing and modifying scan data.